logo-polimi
Loading...
Degree programme
Programme Structure
Show/Search Programme
Degree Programme
International context
Customized Schedule
Your customized time schedule has been disabled
Enable
Search
Search a Professor
Professor's activities
Search a Course
Search a Course (system prior D.M. n. 509)
Search Lessons taught in English
Information on didactic, research and institutional assignments on this page are certified by the University; more information, prepared by the professor, are available on the personal web page and in the curriculum vitae indicated on this webpage.
Information on professor
ProfessorSamori Carlo
QualificationFull professor full time
Belonging DepartmentDipartimento di Elettronica, Informazione e Bioingegneria
Scientific-Disciplinary SectorING-INF/01 - Electronic Engineering
Curriculum VitaeDownload CV (70.29Kb - 17/05/2019)
OrcIDhttps://orcid.org/0000-0002-7084-0721

Contacts
Professor's office hours
DepartmentFloorOfficeDayTimetableTelephoneFaxNotes
Dei - Sede di Via Golgi 40secondo2.16MondayFrom 14:30
To 16:30
0223993732----
E-mailcarlo.samori@polimi.it
Professor's personal website--

Data source: RE.PUBLIC@POLIMI - Research Publications at Politecnico di Milano

List of publications and reserach products for the year 2022 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching (Show >>)
Journal Articles
A Digital PLL with Multi-tap LMS-based Bandwidth Control (Show >>)
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise (Show >>)


List of publications and reserach products for the year 2021 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter (Show >>)
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability (Show >>)
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter (Show >>)
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity (Show >>)
Digital PLLs: The modern timing reference for radar and communication systems (Show >>)
Journal Articles
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter (Show >>)
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping (Show >>)
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs (Show >>)
A Novel Topology of Coupled Phase-Locked Loops (Show >>)


List of publications and reserach products for the year 2020 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Contributions on scientific books
Bang-bang digital PLLs for wireless systems (Show >>)
Conference proceedings
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter (Show >>)
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking (Show >>)
Journal Articles
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL (Show >>)
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking (Show >>)
Jitter Minimization in Digital PLLs with Mid-Rise TDCs (Show >>)


List of publications and reserach products for the year 2019 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS (Show >>)
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power (Show >>)
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS: (Invited Paper) (Show >>)
Journal Articles
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power (Show >>)
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS (Show >>)
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops (Show >>)


List of publications and reserach products for the year 2018 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Contributions on scientific books
Low Power RF Digital PLLs with Direct Carrier Modulation (Show >>)
Conference proceedings
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur (Show >>)
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation (Show >>)
A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs (Show >>)
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range (Show >>)
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators (Show >>)
Digitally-Assisted Frequency Synthesizers for Fast Chirp Generation in mm-Wave radars (Show >>)
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers (Show >>)
Journal Articles
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation (Show >>)
A Background Calibration Technique to Control the Bandwidth of Digital PLLs (Show >>)
manifesti v. 3.4.25 / 3.4.25
Area Servizi ICT
03/07/2022