With this function you can construct your weekly calendar of lessons, which is customized on the basis of the courses that you intend to follow.
Warning: the personal schedule does not replace the presentation of the study plan! It's an informal tool that can help you better manage the organization of class attendance before the study plan presentation.
After the study plan presentation we recommend you to use the Lecture timetable service in your Online Services.
To create your customized schedule follow these instructions:
- Click on the "Enable" link to proceed. You will be asked your surname and first name in order to determine your alphabetic grouping.
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To add or remove courses from your personal schedule, use the small icons which are found next to the courses:
 addition of the course removal of the course selection of the section of the Laboratory of Architecture
(Note: the effective area in which the teaching will be carried out will be determined after the presentation of the Study Plans)
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The sidebar on the left displays the number of lessons included in schedule.
There are also these commands:
 View the schedule: allows the viewing of the weekly synoptic schedule Delete the schedule: cancels the selections made
When you have finished the entry, you can print the calendar you have made.
| Semester (Sem) | | 1 | First Semester | | 2 | Second Semester | | A | Annual course | | (1) | First Half-semester | | (2) | Second Half-semester |
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Language
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Course completely offered in italian
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Course completely offered in english
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Not available
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Note on the teaching activities
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The calculation of the number of students enrolled only considers students enrolled in the academic year in question and does not include any possible students who may be attending but who are enrolled in previous academic years.
In case of structured courses taught by more professors, the number of students enrolled is related to the individual professor module, while the students opinion of the teaching is related to the course as a whole.
The data related to the last academic years (number of students enrolled and students opinion of the teaching) have not yet been defined.
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Information on didactic, research and institutional assignments on this page are certified by the University; more information, prepared by the professor, are available on the personal web page and in the curriculum vitae indicated on this webpage.
| Professor's office hours | | Department | Floor | Office | Day | Timetable | Telephone | Fax | Notes |
|---|
| Dei - Sede di Via Golgi 40 | secondo | 2.16 | Monday | From 14:30
To 16:30 | 0223993732 | -- | -- |
| | E-mail | carlo.samori@polimi.it | | Professor's personal website | -- |
| List of publications and reserach products for the year 2023 (Show all details | Hide all details) |
| Type |
Title of the Publicaiton/Product |
| Conference proceedings |
|
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering (Show >>)(Hide <<)
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| Author/s |
Dartizio, Simone M.; Tesolin, Francesco; Castoro, Giacomo; Buccoleri, Francesco; Lanzoni, Luca; Rossoni, Michele; Cherniak, Dmytro; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore |
| Title of the convention |
2023 IEEE International Solid- State Circuits Conference (ISSCC) |
| Location of the convention |
San Francisco (CA, USA) |
| Title of the review |
--
|
| Pages |
3 - 5 |
| Item link |
http://hdl.handle.net/11311/1233477 |
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4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology (Show >>)(Hide <<)
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| Author/s |
Castoro, Giacomo; Dartizio, Simone M.; Tesolin, Francesco; Buccoleri, Francesco; Rossoni, Michele; Cherniak, Dmytro; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore |
| Title of the convention |
2023 IEEE International Solid- State Circuits Conference (ISSCC) |
| Location of the convention |
San Francisco (CA, USA) |
| Title of the review |
--
|
| Pages |
82 - 84 |
| Item link |
http://hdl.handle.net/11311/1233464 |
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A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS (Show >>)(Hide <<)
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| Author/s |
Ricci, L.; Scaletti, L.; Be', G.; Rocco, M.; Bertulessi, L.; Levantino, S.; Lacaita, A.; Samori, C.; Bonfanti, A. |
| Title of the convention |
VLSI Technology and Circuits |
| Location of the convention |
Kyoto, Japan |
| Period of the convention |
11/06/2023 - 16/06/2023 |
| Title of the review |
--
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| Pages |
1 - 2 |
| Item link |
http://hdl.handle.net/11311/1248698 |
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| Journal Articles |
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A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner (Show >>)(Hide <<)
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| Author/s |
Buccoleri, F; Dartizio, Sm; Tesolin, F; Avallone, L; Santiccioli, A; Iesurum, A; Steffan, G; Cherniak, D; Bertulessi, L; Bevilacqua, A; Samori, C; Lacaita, Al; Levantino, S |
| Title of the review |
IEEE JOURNAL OF SOLID-STATE CIRCUITS (ISSN: 0018-9200) |
| Volume |
58 |
| Brochure |
3 |
| Pages |
634 - 646 |
| Item link |
http://hdl.handle.net/11311/1233414 |
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A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)(Hide <<)
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| Author/s |
Tesolin, Francesco; Dartizio, Simone M.; Buccoleri, Francesco; Santiccioli, Alessio; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore |
| Title of the review |
IEEE JOURNAL OF SOLID-STATE CIRCUITS (ISSN: 0018-9200) |
| Volume |
[Online 2023] |
| Brochure |
-- |
| Pages |
1 - 12 |
| Item link |
http://hdl.handle.net/11311/1245917 |
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| List of publications and reserach products for the year 2022 (Show all details | Hide all details) |
| Type |
Title of the Publicaiton/Product |
| Conference proceedings |
|
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters (Show >>)(Hide <<)
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| Author/s |
Scaletti, Lorenzo; Be', Gabriele; Parisi, Angelo; Bertulessi, Luca; Ricci, Luca; Mercandelli, Mario; Levantino, Salvatore; Samori, Carlo; Bonfanti, ANDREA GIOVANNI |
| Title of the convention |
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) |
| Location of the convention |
Quebec City, Canada |
| Period of the convention |
19-22 June 2022 |
| Title of the review |
--
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| Pages |
20 - 24 |
| Item link |
http://hdl.handle.net/11311/1220934 |
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A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching (Show >>)(Hide <<)
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| Author/s |
Dartizio, S. M.; Buccoleri, F.; Tesolin, F.; Avallone, L.; Santiccioli, A.; Iesurum, A.; Steffan, G.; Cherniak, D.; Bertulessi, L.; Bevilacqua, A.; Samori, C.; Lacaita, A. L.; Levantino, S. |
| Title of the convention |
2022 IEEE International Solid-State Circuits Conference, ISSCC 2022 |
| Location of the convention |
usa |
| Period of the convention |
2022 |
| Title of the review |
--
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| Pages |
386 - 388 |
| Item link |
http://hdl.handle.net/11311/1214731 |
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A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler (Show >>)(Hide <<)
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| Author/s |
Buccoleri, F.; Dartizio, S. M.; Tesolin, F.; Avallone, L.; Santiccioli, A.; Lesurum, A.; Steffan, G.; Bevilacqua, A.; Bertulessi, L.; Cherniak, D.; Samori, C.; Lacaita, A. L.; Levantino, S. |
| Title of the convention |
43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022 |
| Location of the convention |
usa |
| Period of the convention |
2022 |
| Title of the review |
--
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| Pages |
1 - 2 |
| Item link |
http://hdl.handle.net/11311/1218504 |
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Concurrent effect of redundancy and switching algorithms in SAR ADCs (Show >>)(Hide <<)
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| Author/s |
Ricci, Luca; Scaletti, Lorenzo; Be', Gabriele; Bertulessi, Luca; Levantino, Salvatore; Samori, Carlo; Bonfanti, Andrea |
| Title of the convention |
2022 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Location of the convention |
Austin |
| Period of the convention |
27/052022 - 01/06/2022 |
| Title of the review |
--
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| Pages |
900 - 904 |
| Item link |
http://hdl.handle.net/11311/1223741 |
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| Journal Articles |
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A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter (Show >>)(Hide <<)
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| Author/s |
Mercandelli, Mario; Santiccioli, Alessio; Parisi, Angelo; Bertulessi, Luca; Cherniak, Dmytro; Lacaita, Andrea L.; Samori, Carlo; Levantino, Salvatore |
| Title of the review |
IEEE JOURNAL OF SOLID-STATE CIRCUITS (ISSN: 0018-9200) |
| Volume |
57 |
| Brochure |
2 |
| Pages |
505 - 517 |
| Item link |
http://hdl.handle.net/11311/1190014 |
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A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping (Show >>)(Hide <<)
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| Author/s |
Dartizio, Simone M.; Tesolin, Francesco; Mercandelli, Mario; Santiccioli, Alessio; Shehata, Abanob; Karman, Saleh; Bertulessi, Luca; Buccoleri, Francesco; Avallone, Luca; Parisi, Angelo; Lacaita, Andrea L.; Kennedy, Michael P.; Samori, Carlo; Levantino, Salvatore |
| Title of the review |
IEEE JOURNAL OF SOLID-STATE CIRCUITS (ISSN: 0018-9200) |
| Volume |
57 |
| Brochure |
6 |
| Pages |
1723 - 1735 |
| Item link |
http://hdl.handle.net/11311/1187540 |
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A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations (Show >>)(Hide <<)
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| Author/s |
Be', G.; Parisi, A.; Bertulessi, L.; Ricci, L.; Scaletti, L.; Mercandelli, M.; Lacaita, A. L.; Levantino, S.; Samori, C.; Bonfanti, A. |
| Title of the review |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS (ISSN: 1549-7747) |
| Volume |
69 |
| Brochure |
9 |
| Pages |
3645 - 3649 |
| Item link |
http://hdl.handle.net/11311/1218501 |
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A Digital PLL with Multi-tap LMS-based Bandwidth Control (Show >>)(Hide <<)
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| Author/s |
Mercandelli, Mario; Bertulessi, Luca; Samori, Carlo; Levantino, Salvatore |
| Title of the review |
IEEE SOLID-STATE CIRCUITS LETTERS (ISSN: 2573-9603) |
| Volume |
5 |
| Brochure |
-- |
| Pages |
126 - 129 |
| Item link |
http://hdl.handle.net/11311/1214729 |
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A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time (Show >>)(Hide <<)
|
| Author/s |
Dartizio, Simone M.; Buccoleri, Francesco; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Cherniak, Dmytro; Bertulessi, Luca; Bevilacqua, Andrea; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore |
| Title of the review |
IEEE JOURNAL OF SOLID-STATE CIRCUITS (ISSN: 0018-9200) |
| Volume |
57 |
| Brochure |
12 |
| Pages |
3538 - 3551 |
| Item link |
http://hdl.handle.net/11311/1221889 |
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Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise (Show >>)(Hide <<)
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| Author/s |
Bertulessi, Luca; Cherniak, Dmytro; Mercandelli, Mario; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore |
| Title of the review |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS (ISSN: 1549-8328) |
| Volume |
69 |
| Brochure |
5 |
| Pages |
1858 - 1870 |
| Item link |
http://hdl.handle.net/11311/1198859 |
|
| List of publications and reserach products for the year 2021 (Show all details | Hide all details) |
| Type |
Title of the Publicaiton/Product |
| Conference proceedings |
|
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)(Hide <<)
|
| Author/s |
Santiccioli, A.; Mercandelli, M.; Dartizio, S. M.; Tesolin, F.; Karman, S.; Shehata, A.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A.; Cherniak, D.; Lacaita, A. L.; Kennedy, M. P.; Samori, C.; Levantino, S. |
| Title of the convention |
2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 |
| Location of the convention |
usa |
| Period of the convention |
2021 |
| Title of the review |
--
|
| Pages |
456 - 458 |
| Item link |
http://hdl.handle.net/11311/1166752 |
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A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter (Show >>)(Hide <<)
|
| Author/s |
Mercandelli, M.; Santiccioli, A.; Dartizio, S. M.; Shehata, A.; Tesolin, F.; Karman, S.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A.; Lacaita, A. L.; Kennedy, M. P.; Samori, C.; Levantino, S. |
| Title of the convention |
2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 |
| Location of the convention |
usa |
| Period of the convention |
2021 |
| Title of the review |
--
|
| Pages |
446 - 448 |
| Item link |
http://hdl.handle.net/11311/1166753 |
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A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability (Show >>)(Hide <<)
|
| Author/s |
Karman, S.; Tesolin, F.; Dago, A.; Mercandelli, M.; Samori, C.; Levantino, S. |
| Title of the convention |
2021 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2021 |
| Location of the convention |
usa |
| Period of the convention |
2021 |
| Title of the review |
--
|
| Pages |
67 - 70 |
| Item link |
http://hdl.handle.net/11311/1183865 |
|
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A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter (Show >>)(Hide <<)
|
| Author/s |
Mercandelli, Mario; Bertulessi, Luca; Samori, Carlo; Levantino, Salvatore |
| Title of the convention |
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
| Location of the convention |
Busan, Republic of Korea |
| Period of the convention |
7-10 Nov. 2021 |
| Title of the review |
--
|
| Pages |
1 - 3 |
| Item link |
http://hdl.handle.net/11311/1192695 |
|
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A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity (Show >>)(Hide <<)
|
| Author/s |
Parisi, Angelo; Mercandelli, Mario; Samori, Carlo; Lacaita, ANDREA LEONARDO |
| Title of the convention |
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) |
| Location of the convention |
Dubai, United Arab Emirates |
| Title of the review |
--
|
| Pages |
1 - 4 |
| Item link |
http://hdl.handle.net/11311/1194538 |
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Digital PLLs: The modern timing reference for radar and communication systems (Show >>)(Hide <<)
|
| Author/s |
Samori, C.; Bertulessi, L. |
| Title of the convention |
47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 |
| Location of the convention |
Virtual, Online |
| Title of the review |
--
|
| Pages |
21 - 27 |
| Item link |
http://hdl.handle.net/11311/1207537 |
|
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SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends (Show >>)(Hide <<)
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| Author/s |
Amendola, G.; Boccia, L.; Centurelli, F.; Chevalier, P.; Fonte, A.; Karman, S.; Levantino, S.; Mazzanti, A.; Mustacchio, C.; Pallotta, A.; Petricli, I.; Samori, C.; Tesolin, F.; Tommasino, P.; Traversa, A.; Trifiletti, A. |
| Title of the convention |
16th European Microwave Integrated Circuits Conference, EuMIC 2021 |
| Location of the convention |
gbr |
| Period of the convention |
2022 |
| Title of the review |
--
|
| Pages |
113 - 116 |
| Item link |
http://hdl.handle.net/11311/1218502 |
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| Journal Articles |
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A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs (Show >>)(Hide <<)
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| Author/s |
Avallone, L.; Mercandelli, M.; Santiccioli, A.; Kennedy, M. P.; Levantino, S.; Samori, C. |
| Title of the review |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS (ISSN: 1549-8328) |
| Volume |
68 |
| Brochure |
7 |
| Pages |
2775 - 2786 |
| Item link |
http://hdl.handle.net/11311/1172911 |
|
| Author/s |
Karman, Saleh; Tesolin, Francesco; Levantino, Salvatore; Samori, Carlo |
| Title of the review |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS (ISSN: 1549-8328) |
| Volume |
68 |
| Brochure |
3 |
| Pages |
989 - 997 |
| Item link |
http://hdl.handle.net/11311/1161559 |
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| List of publications and reserach products for the year 2020 (Show all details | Hide all details) |
| Type |
Title of the Publicaiton/Product |
| Contributions on scientific books |
| Author/s of the contributin |
Levantino, S.; Samori, C. |
| Title of the book |
Phase-Locked Frequency Generation and Clocking (ISBN: 978-1-78561-885-7; 978-1-78561-886-4) |
| Author/s of the book |
Woogeun Rhee |
| Publisher |
The Institution of Engineering and Technology |
| Pages |
141 - 167 |
| Item link |
http://hdl.handle.net/11311/1142468 |
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| Conference proceedings |
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A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter (Show >>)(Hide <<)
|
| Author/s |
Mercandelli, M.; Santiccioli, A.; Parisi, A.; Bertulessi, L.; Cherniak, D.; Lacaita, A. L.; Samori, C.; Levantino, S. |
| Title of the convention |
2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 |
| Location of the convention |
usa |
| Period of the convention |
2020 |
| Title of the review |
--
|
| Pages |
274 - 276 |
| Item link |
http://hdl.handle.net/11311/1141864 |
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A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking (Show >>)(Hide <<)
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| Author/s |
Santiccioli, A.; Mercandelli, M.; Bertulessi, L.; Parisi, A.; Cherniak, D.; Lacaita, A. L.; Samori, C.; Levantino, S. |
| Title of the convention |
2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 |
| Location of the convention |
usa |
| Period of the convention |
2020 |
| Title of the review |
--
|
| Pages |
268 - 270 |
| Item link |
http://hdl.handle.net/11311/1141865 |
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| Journal Articles |
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A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL (Show >>)(Hide <<)
|
| Author/s |
Cherniak, Dmytro; Mercandelli, Mario; Bertulessi, Luca; Padovan, Fabio; Grimaldi, Luigi; Santiccioli, Alessio; Aichner, Michael; Samori, Carlo; Levantino, Salvatore |
| Title of the review |
IEEE SOLID-STATE CIRCUITS LETTERS (ISSN: 2573-9603) |
| Volume |
3 |
| Brochure |
-- |
| Pages |
126 - 129 |
| Item link |
http://hdl.handle.net/11311/1141867 |
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A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking (Show >>)(Hide <<)
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| Author/s |
Santiccioli, Alessio; Mercandelli, Mario; Bertulessi, Luca; Parisi, Angelo; Cherniak, Dmytro; Lacaita, Andrea L.; Samori, Carlo; Levantino, Salvatore |
| Title of the review |
IEEE JOURNAL OF SOLID-STATE CIRCUITS (ISSN: 0018-9200) |
| Volume |
55 |
| Brochure |
12 |
| Pages |
3349 - 3361 |
| Item link |
http://hdl.handle.net/11311/1145899 |
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Jitter Minimization in Digital PLLs with Mid-Rise TDCs (Show >>)(Hide <<)
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| Author/s |
Avallone, L.; Kennedy, M. P.; Karman, S.; Samori, C.; Levantino, S. |
| Title of the review |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS (ISSN: 1549-8328) |
| Volume |
67 |
| Brochure |
3 |
| Pages |
743 - 752 |
| Item link |
http://hdl.handle.net/11311/1141862 |
|
| List of publications and reserach products for the year 2019 (Show all details | Hide all details) |
| Type |
Title of the Publicaiton/Product |
| Conference proceedings |
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16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS (Show >>)(Hide <<)
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| Author/s |
Grimaldi, Luigi; Bertulessi, Luca; Karman, Saleh; Cherniak, Dmytro; Garghetti, Alessandro; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore |
| Title of the convention |
2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 |
| Location of the convention |
usa |
| Period of the convention |
2019 |
| Title of the review |
--
|
| Pages |
268 - 270 |
| Item link |
http://hdl.handle.net/11311/1081171 |
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A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power (Show >>)(Hide <<)
|
| Author/s |
Santiccioli, A.; Mercandelli, M.; Lacaita, A. L.; Samori, C.; Levantino, S. |
| Title of the convention |
40th Annual IEEE Custom Integrated Circuits Conference (CICC) |
| Location of the convention |
Austin (TX, USA) |
| Period of the convention |
APRIL 14-17, 2019 |
| Title of the review |
--
|
| Pages |
1 - 4 |
| Item link |
http://hdl.handle.net/11311/1104797 |
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Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS: (Invited Paper) (Show >>)(Hide <<)
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| Author/s |
Cherniak, D.; Samori, C.; Levantino, S. |
| Title of the convention |
40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 |
| Location of the convention |
Austin (TX,USA) |
| Period of the convention |
2019 |
| Title of the review |
--
|
| Pages |
1 - 8 |
| Item link |
http://hdl.handle.net/11311/1104800 |
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| Journal Articles |
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A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power (Show >>)(Hide <<)
|
| Author/s |
Santiccioli, Alessio; Mercandelli, Mario; Lacaita, Andrea L.; Samori, Carlo; Levantino, Salvatore |
| Title of the review |
IEEE JOURNAL OF SOLID-STATE CIRCUITS (ISSN: 0018-9200) |
| Volume |
54 |
| Brochure |
11 |
| Pages |
3149 - 3160 |
| Item link |
http://hdl.handle.net/11311/1112456 |
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A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS (Show >>)(Hide <<)
|
| Author/s |
Bertulessi, Luca; Karman, Saleh; Cherniak, Dmytro; Garghetti, Alessandro; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore |
| Title of the review |
IEEE JOURNAL OF SOLID-STATE CIRCUITS (ISSN: 0018-9200) |
| Volume |
54 |
| Brochure |
12 |
| Pages |
3493 - 3502 |
| Item link |
http://hdl.handle.net/11311/1112489 |
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Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops (Show >>)(Hide <<)
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| Author/s |
Santiccioli, Alessio; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore |
| Title of the review |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS (ISSN: 1549-8328) |
| Volume |
66 |
| Brochure |
10 |
| Pages |
3775 - 3785 |
| Item link |
http://hdl.handle.net/11311/1104801 |
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