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Information on didactic, research and institutional assignments on this page are certified by the University; more information, prepared by the professor, are available on the personal web page and in the curriculum vitae indicated on this webpage.
Information on professor
ProfessorLacaita Andrea Leonardo
QualificationFull professor full time
Belonging DepartmentDipartimento di Elettronica, Informazione e Bioingegneria
Scientific-Disciplinary SectorING-INF/01 - Electronic Engineering
Curriculum VitaeDownload CV (381.3Kb - 01/05/2020)
OrcIDhttps://orcid.org/0000-0003-0315-514X

Contacts
Professor's office hours
DepartmentFloorOfficeDayTimetableTelephoneFaxNotes
DEI----MondayFrom 14:00
To 18:00
6117----
E-mailandrea.lacaita@polimi.it
Professor's personal website--

Data source: RE.PUBLIC@POLIMI - Research Publications at Politecnico di Milano

List of publications and reserach products for the year 2024
No product yet registered in the year 2024


List of publications and reserach products for the year 2023 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering (Show >>)
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology (Show >>)
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS (Show >>)
Journal Articles
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner (Show >>)
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering (Show >>)
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)
Phase Noise Analysis of Periodically ON/OFF Switched Oscillators (Show >>)


List of publications and reserach products for the year 2022 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching (Show >>)
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler (Show >>)
Investigation of the Statistical Spread of the Time-Dependent Dielectric Breakdown in Polymeric Dielectrics for Galvanic Isolation (Show >>)
Journal Articles
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter (Show >>)
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping (Show >>)
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations (Show >>)
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time (Show >>)
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology (Show >>)
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise (Show >>)


List of publications and reserach products for the year 2021 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter (Show >>)
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS (Show >>)
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity (Show >>)
High-Density Solid-State Storage: A Long Path to Success (Show >>)
Journal Articles
A Generalization of the Groszkowski’s Result in Differential Oscillator Topologies (Show >>)
Random telegraph noise in 3d nand flash memories (Show >>)
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators (Show >>)


List of publications and reserach products for the year 2020 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Contributions on scientific books
Random Telegraph Noise in Flash Memories (Show >>)
Conference proceedings
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter (Show >>)
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking (Show >>)
Journal Articles
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking (Show >>)
Characterization and Modeling of Current Transport in Metal/Ferroelectric/Semiconductor Tunnel Junctions (Show >>)
Variability Effects in Nanowire and Macaroni MOSFETs—Part I: Random Dopant Fluctuations (Show >>)
Variability Effects in Nanowire and Macaroni MOSFETs—Part II: Random Telegraph Noise (Show >>)
manifesti v. 3.5.13 / 3.5.13
Area Servizi ICT
23/02/2024