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Information on didactic, research and institutional assignments on this page are certified by the University; more information, prepared by the professor, are available on the personal web page and in the curriculum vitae indicated on this webpage.
Information on professor
ProfessorLevantino Salvatore
QualificationFull professor full time
Belonging DepartmentDipartimento di Elettronica, Informazione e Bioingegneria
Scientific-Disciplinary SectorING-INF/01 - Electronic Engineering
Curriculum VitaeDownload CV (455.38Kb - 01/03/2023)
OrcIDhttps://orcid.org/0000-0003-0895-1700

Contacts
Professor's office hours
DepartmentFloorOfficeDayTimetableTelephoneFaxNotes
DEIB - edificio 22Quarto7TuesdayFrom 14:00
To 15:00
0223993731--Please take an appointment
E-mailsalvatore.levantino@polimi.it
Professor's personal websitehttp://levantino.faculty.polimi.it/

Data source: RE.PUBLIC@POLIMI - Research Publications at Politecnico di Milano

List of publications and reserach products for the year 2024 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Journal Articles
Insights on the Dynamic Performance of Nonminimum-Phase Boost Converters Exploiting Inductor-Current-Feedback RHPZ Mitigation (Show >>)


List of publications and reserach products for the year 2023 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Patents
METHOD FOR CONTROLLING A SINGLE INPUT DUAL OUTPUT DC-DC CONVERTER, CORRESPONDING CONVERTER AND COMPUTER PROGRAM PRODUCT (Show >>)
Conference proceedings
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering (Show >>)
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology (Show >>)
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS (Show >>)
A Compact Wide-Input-Range Time-Domain Buck Converter with Fast Transient Response for Industrial Applications (Show >>)
High Power Density 4:1 Resonant Switched-Capacitor DC-DC Converter for PoL Applications (Show >>)
Time-Based Buck Converter with Variable Frequency DCM and ON-Time Correction for Seamless Transitions (Show >>)
Journal Articles
A 1-A 90% Peak Efficiency 5–36-V Input Voltage Time-Based Buck Converter with Adaptive Gain Compensation and Controlled-Skip Operation (Show >>)
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner (Show >>)
A Compact High-Efficiency Boost Converter With Time-Based Control, RHP Zero-Elimination, and Tracking Error Compensation (Show >>)
A High Power Density Quasi-Resonant Switched-Capacitor DC-DC Converter with Single Semi-Period Tank Current Modulation (Show >>)
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering (Show >>)
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)
Integration of loop gain measurement circuit for stability evaluation in DC/DC converters with time-based control (Show >>)
Phase Noise Analysis of Periodically ON/OFF Switched Oscillators (Show >>)
Spread-Spectrum Frequency Modulation in a DC/DC Converter With Time-Based Control (Show >>)


List of publications and reserach products for the year 2022 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Recensioni su riviste
Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC) (Show >>)
Patents
Circuito convertitore DC-DC e corrispondente procedimento di funzionamento (Show >>)
DC-DC CONVERTER APPARATUS WITH TIME-BASED CONTROL LOOP AND CORRESPONDING CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT (Show >>)
RHPZ Mitigation Technique for DC-DC Non-minimum Phase Converter Operating in CCM (Show >>)
Conference proceedings
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters (Show >>)
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching (Show >>)
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler (Show >>)
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation (Show >>)
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters (Show >>)
Concurrent effect of redundancy and switching algorithms in SAR ADCs (Show >>)
Frequency Synthesizers for 5G Applications (Show >>)
Integrated Loop-Gain Measurement Circuit for DC/DC Boost Converters with Time-Based Control (Show >>)
Recent Advances in High-Performance Frequency Synthesizer Design (Show >>)
Journal Articles
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter (Show >>)
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping (Show >>)
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations (Show >>)
A Digital PLL with Multi-tap LMS-based Bandwidth Control (Show >>)
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time (Show >>)
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology (Show >>)
Hybrid Resonant Switched-Capacitor Converter for 48 V to 3.4 V Direct Conversion (Show >>)
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise (Show >>)


List of publications and reserach products for the year 2021 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Patents
CONVERTITORE SWITCHED-CAPACITOR, PROCEDIMENTO, SISTEMA DI ALIMENTAZIONE E DISPOSITIVO ELETTRONICO CORRISPONDENTI (Show >>)
Convertitore DC-DC con anello di controllo basato sul tempo e corrispondente procedimento (Show >>)
Low-Phase-Noise PLL via Reference Path Coupling (Show >>)
PROCEDIMENTO PER IL CONTROLLO DI UN CONVERTITORE DC-DC SINGLE INPUT DUAL OUTPUT, CORRISPONDENTE CONVERTITORE E PRODOTTO INFORMATICO (Show >>)
Conference proceedings
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter (Show >>)
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS (Show >>)
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability (Show >>)
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter (Show >>)
An 800-mA Time-Based Boost Converter in 0.18um BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency (Show >>)
SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends (Show >>)
Journal Articles
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs (Show >>)
A Novel Topology of Coupled Phase-Locked Loops (Show >>)


List of publications and reserach products for the year 2020 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Contributions on scientific books
Bang-bang digital PLLs for wireless systems (Show >>)
Chirp Generators for Millimeter-Wave FMCW Radars (Show >>)
Conference proceedings
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter (Show >>)
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking (Show >>)
A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM/PWM Transition (Show >>)
Journal Articles
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL (Show >>)
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking (Show >>)
Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing (Show >>)
Jitter Minimization in Digital PLLs with Mid-Rise TDCs (Show >>)
manifesti v. 3.5.13 / 3.5.13
Area Servizi ICT
28/02/2024