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Information on didactic, research and institutional assignments on this page are certified by the University; more information, prepared by the professor, are available on the personal web page and in the curriculum vitae indicated on this webpage.
Information on professor
ProfessorLevantino Salvatore
QualificationFull professor full time
Belonging DepartmentDipartimento di Elettronica, Informazione e Bioingegneria
Scientific-Disciplinary SectorING-INF/01 - Electronic Engineering
Curriculum VitaeDownload CV (317.24Kb - 25/10/2019)
OrcIDhttps://orcid.org/0000-0003-0895-1700

Contacts
Professor's office hours
DepartmentFloorOfficeDayTimetableTelephoneFaxNotes
DEIB - edificio 22Quarto7TuesdayFrom 14:00
To 15:00
0223993731--Please take an appointment
E-mailsalvatore.levantino@polimi.it
Professor's personal websitehttp://levantino.faculty.polimi.it/

Data source: RE.PUBLIC@POLIMI - Research Publications at Politecnico di Milano

List of publications and reserach products for the year 2022 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters (Show >>)
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching (Show >>)
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler (Show >>)
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation (Show >>)
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters (Show >>)
Integrated Loop-Gain Measurement Circuit for DC/DC Boost Converters with Time-Based Control (Show >>)
Recent Advances in High-Performance Frequency Synthesizer Design (Show >>)
Journal Articles
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations (Show >>)
A Digital PLL with Multi-tap LMS-based Bandwidth Control (Show >>)
Hybrid Resonant Switched-Capacitor Converter for 48 V to 3.4 V Direct Conversion (Show >>)
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise (Show >>)


List of publications and reserach products for the year 2021 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Patents
Low-Phase-Noise PLL via Reference Path Coupling (Show >>)
Conference proceedings
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter (Show >>)
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS (Show >>)
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability (Show >>)
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter (Show >>)
An 800-mA Time-Based Boost Converter in 0.18um BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency (Show >>)
SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends (Show >>)
Journal Articles
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter (Show >>)
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping (Show >>)
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs (Show >>)
A Novel Topology of Coupled Phase-Locked Loops (Show >>)
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology (Show >>)


List of publications and reserach products for the year 2020 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Contributions on scientific books
Bang-bang digital PLLs for wireless systems (Show >>)
Chirp Generators for Millimeter-Wave FMCW Radars (Show >>)
Conference proceedings
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter (Show >>)
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking (Show >>)
A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM/PWM Transition (Show >>)
Journal Articles
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL (Show >>)
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking (Show >>)
Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing (Show >>)
Jitter Minimization in Digital PLLs with Mid-Rise TDCs (Show >>)


List of publications and reserach products for the year 2019 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Patents
RADAR SIGNAL MODULATOR WITH BANDWIDTH COMPENSATION AND FREQUENCY OFFSET SEQUENCE (Show >>)
Conference proceedings
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS (Show >>)
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power (Show >>)
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS: (Invited Paper) (Show >>)
Journal Articles
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power (Show >>)
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS (Show >>)
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops (Show >>)


List of publications and reserach products for the year 2018 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Patents
Schaltung mit Oszillatoren, Phasenregelkreis-Schaltung und Verfahren (Show >>)
Contributions on scientific books
Low Power RF Digital PLLs with Direct Carrier Modulation (Show >>)
Conference proceedings
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur (Show >>)
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation (Show >>)
A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique (Show >>)
A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs (Show >>)
A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-Injection (Show >>)
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range (Show >>)
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators (Show >>)
Digital phase-locked loops (Show >>)
Digitally-Assisted Frequency Synthesizers for Fast Chirp Generation in mm-Wave radars (Show >>)
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers (Show >>)
Journal Articles
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation (Show >>)
A Background Calibration Technique to Control the Bandwidth of Digital PLLs (Show >>)
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking (Show >>)
Variation-aware Modeling of Integrated Capacitors based on Floating Random Walk Extraction (Show >>)
manifesti v. 3.4.30 / 3.4.30
Area Servizi ICT
07/10/2022