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Le informazioni sulla didattica, sulla ricerca e sui compiti istituzionali riportate in questa pagina sono certificate dall'Ateneo; ulteriori informazioni, redatte a cura del docente, sono disponibili sulla pagina web personale e nel curriculum vitae indicati nella scheda.
Informazioni sul docente
DocenteLevantino Salvatore
QualificaProfessore ordinario a tempo pieno
Dipartimento d'afferenzaDipartimento di Elettronica, Informazione e Bioingegneria
Settore Scientifico DisciplinareING-INF/01 - Elettronica
Curriculum VitaeScarica il CV (317.24Kb - 25/10/2019)
OrcIDhttps://orcid.org/0000-0003-0895-1700

Contatti
Orario di ricevimento
DipartimentoPianoUfficioGiornoOrarioTelefonoFaxNote
DEIB - edificio 22Quarto7MartedìDalle 14:00
Alle 15:00
0223993731--Per appuntamento
E-mailsalvatore.levantino@polimi.it
Pagina web redatta a cura del docentehttp://levantino.faculty.polimi.it/

Fonte dati: RE.PUBLIC@POLIMI - Research Publications at Politecnico di Milano

Elenco delle pubblicazioni e dei prodotti della ricerca per l'anno 2023 (Mostra tutto | Nascondi tutto)
Tipologia Titolo Pubblicazione/Prodotto
Articoli su riviste
A Compact High-Efficiency Boost Converter With Time-Based Control, RHP Zero-Elimination, and Tracking Error Compensation (Mostra >>)


Elenco delle pubblicazioni e dei prodotti della ricerca per l'anno 2022 (Mostra tutto | Nascondi tutto)
Tipologia Titolo Pubblicazione/Prodotto
Recensioni su riviste
Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC) (Mostra >>)
Contributo in Atti di convegno
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters (Mostra >>)
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching (Mostra >>)
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler (Mostra >>)
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation (Mostra >>)
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters (Mostra >>)
Concurrent effect of redundancy and switching algorithms in SAR ADCs (Mostra >>)
Frequency Synthesizers for 5G Applications (Mostra >>)
Integrated Loop-Gain Measurement Circuit for DC/DC Boost Converters with Time-Based Control (Mostra >>)
Recent Advances in High-Performance Frequency Synthesizer Design (Mostra >>)
Articoli su riviste
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations (Mostra >>)
A Digital PLL with Multi-tap LMS-based Bandwidth Control (Mostra >>)
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time (Mostra >>)
Hybrid Resonant Switched-Capacitor Converter for 48 V to 3.4 V Direct Conversion (Mostra >>)
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise (Mostra >>)
Phase Noise Analysis of Periodically ON/OFF Switched Oscillators (Mostra >>)


Elenco delle pubblicazioni e dei prodotti della ricerca per l'anno 2021 (Mostra tutto | Nascondi tutto)
Tipologia Titolo Pubblicazione/Prodotto
Brevetti
Low-Phase-Noise PLL via Reference Path Coupling (Mostra >>)
Contributo in Atti di convegno
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays (Mostra >>)
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter (Mostra >>)
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS (Mostra >>)
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability (Mostra >>)
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter (Mostra >>)
An 800-mA Time-Based Boost Converter in 0.18um BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency (Mostra >>)
SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends (Mostra >>)
Articoli su riviste
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter (Mostra >>)
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping (Mostra >>)
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs (Mostra >>)
A Novel Topology of Coupled Phase-Locked Loops (Mostra >>)
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology (Mostra >>)


Elenco delle pubblicazioni e dei prodotti della ricerca per l'anno 2020 (Mostra tutto | Nascondi tutto)
Tipologia Titolo Pubblicazione/Prodotto
Contributi su volumi (Capitolo o Saggio)
Bang-bang digital PLLs for wireless systems (Mostra >>)
Chirp Generators for Millimeter-Wave FMCW Radars (Mostra >>)
Contributo in Atti di convegno
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter (Mostra >>)
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking (Mostra >>)
A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM/PWM Transition (Mostra >>)
Articoli su riviste
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL (Mostra >>)
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking (Mostra >>)
Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing (Mostra >>)
Jitter Minimization in Digital PLLs with Mid-Rise TDCs (Mostra >>)


Elenco delle pubblicazioni e dei prodotti della ricerca per l'anno 2019 (Mostra tutto | Nascondi tutto)
Tipologia Titolo Pubblicazione/Prodotto
Brevetti
RADAR SIGNAL MODULATOR WITH BANDWIDTH COMPENSATION AND FREQUENCY OFFSET SEQUENCE (Mostra >>)
Contributo in Atti di convegno
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS (Mostra >>)
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power (Mostra >>)
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS: (Invited Paper) (Mostra >>)
Articoli su riviste
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power (Mostra >>)
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS (Mostra >>)
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops (Mostra >>)
manifesti v. 3.5.4 / 3.5.4
Area Servizi ICT
30/01/2023